This application claims the priority of Korean Patent Application No. 2003-68321, filed on Oct. 1, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a bonding medium, a method of manufacturing the same, and a method of bonding two parts using the method of manufacturing the bonding medium, and more particularly, to a SnAgAu solder bump and a method of manufacturing the same, and a method of bonding a light emitting device using the solder bump.
2. Description of the Related Art
Wire bonding has been widely used for bonding a light emitting device and a submount. The wire bonding between a light emitting device and a submount is performed not only to apply a driving voltage to the light emitting device, but also to remove heat generated by the light emitting device during its operation.
In light emitting devices such as LDs or LEDs, it is preferable for a channel through which current is supplied to have a low resistance, in order to keep the driving voltage at a low level. In addition, it is preferable for heat generated by the light emitting devices to be removed rapidly.
Meanwhile, as the integration density of chips including light emitting devices increases, the length of wires connecting the light emitting devices to submounts seems to be increased.
Because a line resistance of the wires connecting the light emitting devices to the submounts is proportional to the wire's length, the increased length of the wires is accompanied by increased resistance.
Therefore, when current is provided to the light emitting devices via the wires, the driving voltage is increased. Additionally, when heat from the light emitting devices is removed via the wires, heat removal efficiency is decreased, ultimately leading to further increase in the driving voltage of the light emitting devices.
Accordingly, flip-chip bonding has been recently used instead of wire bonding between a light emitting device and a submount.
When a light emitting device is connected to a submount using the flip-chip bonding, heat resistance and line resistance are lower than in the case of wire boning, because they are directly connected via solder bumps.
FIG. 1 illustrates conventional technology in which a light emitting device is bonded to a submount using the flip-chip bonding.
Referring to FIG. 1, reference numerals 14 and 16 denote a light emitting device and a submount, respectively. The light emitting device 14 is flipped to be bonded to the submount 16. The light emitting device 14 includes a compound semiconductor layer 12 and a substrate on which the semiconductor layer 12 is formed. The compound semiconductor layer 12 includes, for example, an n-type compound semiconductor layer (not shown), a p-type compound semiconductor layer (not shown) and an active layer interposed therebetween. First and second pad layers 22a and 22b are formed on the submount 16 and separated from one another. The first and second pad layers 22a and 22b faces two regions of the compound semiconductor layer 12, respectively: one region where an n-type electrode (not shown) is formed, and the other region (protruding toward the submount 16) where a p-type electrode (not shown) is formed. A step S is formed between the two regions. A pad layer 18a, which contacts the n-type electrode, is formed in the region of the compound semiconductor layer 12 where the n-type electrode is formed, and a pad layer 18b, which contacts the p-type electrode, is formed in the region of the compound semiconductor layer 12 where the p-type electrode is formed. In addition, a portion of a surface of the pad layer 18a facing the submount 16 that contacts n-type electrode is covered with a first Au film 20a, and a portion of a surface of the pad layer 18b facing the submount 16 that contacts the p-type electrode is covered with a second Au film 20b. 
A first Pt film 24a is formed on an upper surface of the first pad layer 22a deposited on the submount 16, and a second Pt film 24b is formed on an upper surface of the second pad layer 22b. The first Pt film 24a faces the first Au film 20a, and the second Pt film 24b faces the second Au film 20b. The first Pt film 24a is connected to the first Au film 20a by a first AuSn solder bump 26a, and the second Pt film 24b is connected to the second Au film 20b by a second AnSn solder bump 26b. The first and second Pt films 24a and 24b prevent diffusion of Sn from the first and second AnSn solder bumps 26a and 26b into the first and second pad layers 22a and 22b. 
In the conventional technology described above, the first and second AuSn solder bumps 26a and 26b are formed by heating AuSn solder at a temperature of 280° C. or more for a few seconds. When the AuSn solder is heated at a temperature of 280° C. or more, characteristics of a metal layer for the p-type electrode change. As a result, the contact resistance of the p-type electrode increases, leading to an increase in the driving voltage of the light emitting device.